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Electrical/thermal analysis in the DC domain

With Cadence® Sigrity™ PowerDC™, you get added accuracy of electrical/thermal co-simulation, as well as the assurance that your PDN performs as expected. With PowerDC, you can easily locate accidental voltage losses, high current densities, via with excessive currents and thermal hotspots. All these effects can significantly affect the quality of the design and limit the life of the product.

Book demo

Identify critical points

Identify critical points in the layout where narrowings in traces or planes give too much current density and easily find the one among thousands that is the weakest point.

Detailed analysis

Perform detailed analysis of stackup parameters such as copper thicknesses and number of layers without risking electrical or thermal problems.

Fast and accurate

Avoid errors with a very accurate simulation and go into details in every detail of the design. 


Companies using Sigrity - Signal & Power Integrity

IQM uses AWR to make RF/microwave chips for quantum computers. We also use AWR to design RF matching circuits and components such as filters and I think AWR offers good opportunities to speed up our efforts for all of this.
Jaakko Jussila
Team Leader, IQM Quantum Computers
With the help of Nordcad, we built a cloud solution for our licenses so that they can be accessed no matter where we are in the world. In addition, Nordcad offers a flexible solution that makes it possible to grow without investment. This has enabled us to support customers from day 1. You always feel like part of the family at Nordcad. If you come up with a problem, the support is fantastic and you really feel like you get help right away.
Steen Kaare Grøndahl
Founder and CEO, Wise Choice Consulting ApS

Complete frequency characteristic and optimisation of PDN

With Cadence® Sigrity™ OptimizePI™, you get insight into how the PDN frequency characteristics look for each individual component, including the planes shape and placement in the stackup, decoupling their routing and placement, as well as routing from supply plans to components. Decouplings can also be optimised in terms of price vs. performance and verify EMI performance by measuring impedance for self-selected locations on the layout.

  • Avoid costly over-design of PDN based rules or data sheet descriptions
  • Optimise the PDN based on the actual layout instead of a simplified model in a spreadsheet
  • Unique possibility for analysis of PDN impedance for components and EMI resonance for planes
  • Make fast assessments of PDN performance based on easily accessible results
Get in touch
+45 96 31 56 90

Power-Aware signal integrity

Simultaneous switching noise (SSN) can change the timing on a memory interface. With Sigrity™ Power-Aware SI, you get a complete solution for analysing source-synchronous interfaces used for e.g. DDR3 and DDR4 memory interfaces. Power-Aware SI includes both tools for layout extraction of traces and supply voltage, as well as intuitive simulation tools for parallel bus analysis that can generate reports with information on time margins being met according to the JEDEC standard.
Book demo

Simultaneous Switching noise (SSN)

Simultaneous switching noise (SSN) can change the timing on a memory interface.

Intuitive simulation tool

Power-Aware SI includes both tools for layout extraction of traces and supply voltage as well as intuitive simulation tools for parallel bus analysis that can generate reports with information on time margins being met according to the JEDEC standard.

Serial link analysis

Perform chip-to-chip analysis on your High-Speed SerDes interfaces, such as PCI Express® (PCIe®), HDMI, SFP+, Xaui, Infiniband, SAS, SATA, and USB with industry-standard IBIS AMI models. You can perform pre-layout analyses using templates and along the way add models of component packages, connectors, and layouts to reflect the entire interface. Simulations can be used to identify crosstalk problems and show not only the signals in the interface, but also signals after clock and data recovery (CDR), which are described in the IBIS AMI model. By simulating the complete interface with millions of bits, the overall bit error rate (BER) can be calculated to determine whether jitter and noise levels are within specified tolerances.

Learn more about Sigrity or request a free trial

Want to hear about your possibilities with Nordcad? Reach out to our specialists for a preliminary casual chat.

    Søren  Jul Christiansen
    Senior Application Engineer
    sjc@nordcad.dk+45 96 31 56 98
    Arvid Thorndahl
    Senior Partner
    at@nordcad.dk+45 96 31 56 93
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